threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
46 lines
1.8 KiB
Plaintext
46 lines
1.8 KiB
Plaintext
Binding for Texas Instruments APLL clock.
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. It assumes a
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register-mapped APLL with usually two selectable input clocks
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(reference clock and bypass clock), with analog phase locked
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loop logic for multiplying the input clock to a desired output
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clock. This clock also typically supports different operation
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modes (locked, low power stop etc.) APLL mostly behaves like
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a subtype of a DPLL [2], although a simplified one at that.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
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Required properties:
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- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
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- reg : address and length of the register set for controlling the APLL.
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It contains the information of registers in the following order:
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"control" - contains the control register offset
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"idlest" - contains the idlest register offset
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"autoidle" - contains the autoidle register offset (OMAP2 only)
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- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
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- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
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- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
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Examples:
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apll_pcie_ck: apll_pcie_ck {
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#clock-cells = <0>;
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clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
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reg = <0x021c>, <0x0220>;
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compatible = "ti,dra7-apll-clock";
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};
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apll96_ck: apll96_ck {
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#clock-cells = <0>;
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compatible = "ti,omap2-apll-clock";
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clocks = <&sys_ck>;
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ti,bit-shift = <2>;
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ti,idlest-shift = <8>;
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ti,clock-frequency = <96000000>;
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reg = <0x0500>, <0x0530>, <0x0520>;
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};
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