threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
51 lines
1.4 KiB
Plaintext
51 lines
1.4 KiB
Plaintext
* HiSilicon Clock and Reset Generator(CRG)
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The CRG module provides clock and reset signals to various
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modules within the SoC.
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This binding uses the following bindings:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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Documentation/devicetree/bindings/reset/reset.txt
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Required Properties:
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- compatible: should be one of the following.
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- "hisilicon,hi3516cv300-crg"
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- "hisilicon,hi3516cv300-sysctrl"
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- "hisilicon,hi3519-crg"
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- "hisilicon,hi3798cv200-crg"
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- "hisilicon,hi3798cv200-sysctrl"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
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- #reset-cells: should be 2.
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A reset signal can be controlled by writing a bit register in the CRG module.
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The reset specifier consists of two cells. The first cell represents the
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register offset relative to the base address. The second cell represents the
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bit index in the register.
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Example: CRG nodes
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CRG: clock-reset-controller@12010000 {
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compatible = "hisilicon,hi3519-crg";
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reg = <0x12010000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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};
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Example: consumer nodes
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i2c0: i2c@12110000 {
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compatible = "hisilicon,hi3519-i2c";
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reg = <0x12110000 0x1000>;
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clocks = <&CRG HI3519_I2C0_RST>;
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resets = <&CRG 0xe4 0>;
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};
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