threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
51 lines
1.5 KiB
Plaintext
51 lines
1.5 KiB
Plaintext
* Samsung Exynos5410 Clock Controller
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The Exynos5410 clock controller generates and supplies clock to various
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controllers within the Exynos5410 SoC.
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Required Properties:
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- compatible: should be "samsung,exynos5410-clock"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- clocks: should contain an entry specifying the root clock from external
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oscillator supplied through XXTI or XusbXTI pin. This clock should be
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defined using standard clock bindings with "fin_pll" clock-output-name.
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That clock is being passed internally to the 9 PLLs.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos5410.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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fin_pll: xxti {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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};
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clock: clock-controller@0x10010000 {
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compatible = "samsung,exynos5410-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@12C20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <0 51 0>;
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clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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};
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