threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
47 lines
1.6 KiB
Plaintext
47 lines
1.6 KiB
Plaintext
SP810 System Controller
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-----------------------
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Required properties:
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- compatible: standard compatible string for a Primecell peripheral,
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see Documentation/devicetree/bindings/arm/primecell.txt
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for more details
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should be: "arm,sp810", "arm,primecell"
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- reg: standard registers property, physical address and size
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of the control registers
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- clock-names: from the common clock bindings, for more details see
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Documentation/devicetree/bindings/clock/clock-bindings.txt;
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should be: "refclk", "timclk", "apb_pclk"
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- clocks: from the common clock bindings, phandle and clock
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specifier pairs for the entries of clock-names property
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- #clock-cells: from the common clock bindings;
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should be: <1>
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- clock-output-names: from the common clock bindings;
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should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
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- assigned-clocks: from the common clock binding;
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should be: clock specifier for each output clock of this
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provider node
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- assigned-clock-parents: from the common clock binding;
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should be: phandle of input clock listed in clocks
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property with the highest frequency
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Example:
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v2m_sysctl: sysctl@020000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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};
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