threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
40 lines
1.2 KiB
Plaintext
40 lines
1.2 KiB
Plaintext
Broadcom Northstar Plus SoC CPU Enable Method
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---------------------------------------------
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This binding defines the enable method used for starting secondary
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CPU in the following Broadcom SoCs:
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BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
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The enable method is specified by defining the following required
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properties in the corresponding secondary "cpu" device tree node:
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- enable-method = "brcm,bcm-nsp-smp";
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- secondary-boot-reg = <...>;
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The secondary-boot-reg property is a u32 value that specifies the
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physical address of the register which should hold the common
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entry point for a secondary CPU. This entry is cpu node specific
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and should be added per cpu. E.g., in case of NSP (BCM58625) which
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is a dual core CPU SoC, this entry should be added to cpu1 node.
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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enable-method = "brcm,bcm-nsp-smp";
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secondary-boot-reg = <0xffff042c>;
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reg = <1>;
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};
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};
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